The technological development of micro-sized semiconductor integrated circuit devices has required improved methods for making conductive contacts to the semiconductor impurity regions. Metal silicides have proven to be excellent contact materials, which can be readily formed in a self-aligned manner by a salicidation process.
Formation of metal silicide contacts through the salicidation process typically involves the steps of depositing a thin metal layer (e.g., less than about 15 nm in thickness) that contains a silicide metal or metal alloy (i.e., a metal or metal alloy that is capable of reacting with silicon to form metal silicide) uniformly over a semiconductor substrate that contains both silicon-containing device regions and dielectric isolation regions, heating the semiconductor substrate to form silicide over the device regions, and then selectively etching away the unreacted metal from the dielectric isolation regions. For successful fabrication of high performance semiconductor devices, the etching should be highly selective, i.e., it removes all unreacted metal or metal alloy from the dielectric isolation regions, without attacking or otherwise damaging the silicide on the device regions.
Nickel or nickel alloy, such as nickel-platinum alloy, have been commonly used as the silicide metal for forming the silicide contacts in the CMOS technology.
Specifically, for forming pure nickel silicide contacts, a rapid thermal annealing (RTA) step is typically employed to convert the deposited thin nickel layer located on the device regions into nickel silicide, followed by a nickel-etching step to remove the unreacted nickel from the dielectric isolation regions. However, residual material, probably nickel silicide, tends to form over the dielectric isolation regions after the RTA step. Such residual material cannot be satisfactorily removed by the etchant(s) used in the nickel-etching step. The presence of residue material on the dielectric isolation region significantly increases the risk of shorting between device regions and reduces the device reliability. This problem becomes more severe as the RTA temperature increases.
Further, for forming silicide contacts that contain nickel silicide as well as one or more other metal silicides, such as platinum silicide and/or rhenium silicide, a nickel alloy layer that contains nickel and one or more additional silicide metals, such as platinum and/or rhenium, is deposited over the semiconductor substrate. An RTA step is also employed to convert nickel and platinum/rhenium into nickel silicide and platinum/rhenium silicide in the device regions, followed by an aqua regia (AR) etching step to remove both the unreacted nickel and platinum/rhenium from the dielectric isolation regions. Similar problem exists due to presence of residual material over the dielectric isolation regions after the RTA step.
Moreover, when the RTA temperature equals or is less than about 400° C., the silicides formed by the RTA is highly susceptible to attacks by the AR etchant, and significant damages to the silicide contacts may result during the AR etching. On the other hand, when the RTA is carried out at a higher temperature (e.g., >600° C.), gross formation of residual material is observed over the dielectric isolation regions. FIGS. 1A and 1B illustrate silicon contacts formed by conventional RTA/AR etching processes. Specifically, silicide contacts 3 and 5, which preferably contain nickel silicide and platinum silicide, are formed over a semiconductor substrate 1 that includes two silicon-containing semiconductor device regions 2 and 4 with a dielectric isolation region 6 therebetween. When the RTA temperature is not high enough, the silicide contacts 3 and 5 will be severely damaged by the AR etching, thereby resulting in a very irregular surface morphology, as shown in FIG. 1A. On the other hand, when the RTA temperature is higher, residual materials (e.g., nickel-platinum-silicide), which are denoted by layer 7, can be formed over the dielectric isolation region 6, as shown in FIG. 1B.
There is therefore a continuing need for an improved method for fabricating the silicide contacts on semiconductor substrates, which is capable of both minimizing the formation of residual materials on the dielectric isolation regions and reducing etching damages to the silicide contacts.